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11.3 Gbps, Active Back-Termination, Differential Laser Diode Driver ADN2531
FEATURES
3.3 V operation Up to 11.3 Gbps operation Typical 26 ps rise/fall times Bias current range: 10 mA to 100 mA Differential modulation current range: 10 mA to 80 mA Voltage input control for bias and modulation currents Data inputs sensitivity: 150 mV p-p differential Automatic laser shutdown (ALS) Crosspoint adjustment (CPA) VCSEL, FP, DFB laser support SFF/SFP/XFP/SFP+ MSA compliant Optical evaluation board available Compact, 3 mm x 3 mm LFCSP
GENERAL DESCRIPTION
The ADN2531 laser diode driver can work with directly modulated laser diodes, including vertical-cavity surface-emitting laser (VCSEL), Fabry-Perot (FP) lasers, and distributed feedback (DFB) lasers, with a differential loading resistance ranging from 5 to 140 . The active back-termination in the ADN2531 absorbs signal reflections from the laser diode side of the output transmission lines, enabling excellent optical eye quality even when the TOSA end of the output transmission lines is significantly mismatched. The ADN2531 is a SFP+ MSA-compliant device, and its small package and enhanced ESD protection provides the optimum solution for compact modules in which laser diodes are packaged in low pin-count optical subassemblies. The modulation and bias currents are programmable via the MSET and BSET control pins. By driving these pins with control voltages, the user has the flexibility to implement various average optical power and extinction ratio control schemes, including a closed-loop or a look-up table control. The automatic laser shutdown (ALS) feature allows turning the bias on and off while simultaneously modulating currents by driving the ALS pin with a low voltage transistor-to-transistor logic (LVTTL) source. The product is available in a space-saving, 3 mm x 3 mm LFCSP package and operates from -40C to +100C.
APPLICATIONS
Optical transmitters, up to 11.3 Gbps, for SONET/SDH, Ethernet, and Fibre Channel applications SFF/SFP/SFP+/XFP/X2/XENPAK/XPAK MSA compliant 300-pin optical modules, up to 11.3 Gbps
FUNCTIONAL BLOCK DIAGRAM
VCC VCC VCC CPA ALS
ADN2531
IMODP 100 IMOD IMODN VCC
50
50 GND
DATAP DATAN
CROSSPOINT ADJUST
IBMON IBIAS 400 800
200
200
200
10
07881-001
MSET
GND
BSET
Figure 1.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 (c)2009 Analog Devices, Inc. All rights reserved.
ADN2531 TABLE OF CONTENTS
Features .............................................................................................. 1 Applications ....................................................................................... 1 General Description ......................................................................... 1 Functional Block Diagram .............................................................. 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 Package Thermal Specifications ................................................. 4 Absolute Maximum Ratings............................................................ 5 ESD Caution .................................................................................. 5 Pin Configuration and Function Descriptions ............................. 6 Typical Performance Characteristics ............................................. 7 Test Circuit ...................................................................................... 10 Theory of Operation ...................................................................... 11 Input Stage ................................................................................... 11 Bias Current ................................................................................ 11 Automatic Laser Shutdown (ALS) ........................................... 12 Modulation Current ................................................................... 12 Load Mistermination ................................................................. 14 Crosspoint Adjust ....................................................................... 14 Power Consumption .................................................................. 14 Applications Information .............................................................. 15 Typical Application Circuit ....................................................... 15 Layout Guidelines....................................................................... 16 Design Example .......................................................................... 16 Outline Dimensions ....................................................................... 18 Ordering Guide .......................................................................... 18
REVISION HISTORY
9/09--Revision 0: Initial Version
Rev. 0 | Page 2 of 20
ADN2531 SPECIFICATIONS
VCC = VCCMIN to VCCMAX, TA = -40C to +100C, 12 differential load impedance, crosspoint adjust disabled, unless otherwise noted. Typical values are specified at 25C and IBIAS = IMOD = 40 mA with crosspoint adjust disabled, unless otherwise noted. Table 1.
Parameter BIAS CURRENT (IBIAS) Bias Current Range Bias Current While ALS Asserted Compliance Voltage 1 MODULATION CURRENT (IMODP, IMODN) Modulation Current IMOD Range IMOD While ALS Asserted Crosspoint Adjust (CPA) Range 2 Rise Time (20% to 80%)2, 3, 4 Fall Time (20% to 80%)2, 3, 4 Random Jitter2, 3, 4 Deterministic Jitter2, 4, 5 Deterministic Jitter 2, 4, 6 Differential |S22| Compliance Voltage1 DATA INPUTS (DATAP, DATAN) Input Data Rate Differential Input Swing Differential |S11| Input Termination Resistance BIAS CONTROL INPUT (BSET) BSET Voltage to IBIAS Gain BSET Input Resistance MODULATION CONTROL INPUT (MSET) MSET Voltage to IMOD Gain MSET Input Resistance BIAS MONITOR (IBMON) IBMON to IBIAS Ratio Accuracy of IBIAS to IBMON Ratio VCC - 1.1 Min 10 0.6 0.55 10 70 35 26 26 <0.5 5.4 5.8 5.4 5.8 -5 -10.5 500 65 32.5 32.5 8.2 8.2 8.2 8.2 Typ Max 100 300 VCC VCC 80 Unit mA A V V mA diff mA diff A diff % ps ps ps rms ps p-p ps p-p ps p-p ps p-p dB dB V Gbps V p-p diff dB mA/V mA/V A/mA % % % % V V A A s s Test Conditions/Comments
ALS = high IBIAS = 80 mA IBIAS = 10 mA RLOAD = 5 to 50 differential RLOAD = 100 differential ALS = high
10.7 Gbps, CPA disabled 10.7 Gbps, CPA 35% to 65% 11.3 Gbps, CPA disabled 11.3 Gbps, CPA 35% to 65% 5 GHz < f < 10 GHz, Z0 = 100 differential 7 f < 5 GHz, Z0 = 100 differential7
VCC + 1.1 11.3 1.6 -15 100 100 1000 120 600 10 115
0.15 85
NRZ Differential ac-coupled f < 10 GHz, Z0 = 100 differential Differential
800
1200
-5.0 -4.0 -2.5 -2 2.0 -20 0
+5.0 +4.0 +2.5 +2
10 mA IBIAS < 20 mA, RIBMON = 750 20 mA IBIAS < 40 mA, RIBMON = 750 40 mA IBIAS < 70 mA, RIBMON = 750 70 mA IBIAS < 80 mA, RIBMON = 750
AUTOMATIC LASER SHUTDOWN (ALS) VIH VIL IIL IIH ALS Assert Time ALS Negate Time
0.8 +20 200 2 10
Rising edge of ALS to falling edge of IBIAS and IMOD below 10% of nominal; see Figure 2 Falling edge of ALS to rising edge of IBIAS and IMOD above 90% of nominal; see Figure 2
Rev. 0 | Page 3 of 20
ADN2531
Parameter POWER SUPPLY VCC ICC 8 ISUPPLY 9
1 2 3
Min 3.0
Typ 3.3 36 55
Max 3.6 62
Unit V mA mA
Test Conditions/Comments
VBSET = VMSET = 0 V VBSET = VMSET = 0 V
The voltage between the pin with the specified compliance voltage and GND. Specified for TA = -40C to +85C due to test equipment limitation. See the Typical Performance Characteristics section for data on performance for TA = -40C to +100C. The pattern used is composed of a repetitive sequence of eight 1s followed by eight 0s at 10.7 Gbps. 4 Measured using the high speed characterization circuit shown in Figure 22. 5 The pattern used is K28.5 (00111110101100000101) at 10.7 Gbps rate. 6 The pattern used is K28.5 (00111110101100000101) at 11.3 Gbps rate. 7 Measured at balanced IMODP and IMODN. 8 Only includes current in the ADN2531 VCC pins. 9 Includes current in ADN2531 VCC pins and dc current in IMODP and IMODN pull-up inductors. See the Power Consumption section for total supply current calculation.
PACKAGE THERMAL SPECIFICATIONS
Table 2.
Parameter J-TOP J-PAD IC Junction Temperature Min 65 2.6 Typ 72.2 5.8 Max 79.4 10.7 125 Unit C/W C/W C Test Conditions/Comments Thermal resistance from junction to top of package. Thermal resistance from junction to bottom of exposed pad.
ALS
ALS NEGATE TIME
t IBIAS AND I MOD 90%
10%
t
07881-002
ALS ASSERT TIME
Figure 2. ALS Timing Diagram
Rev. 0 | Page 4 of 20
ADN2531 ABSOLUTE MAXIMUM RATINGS
Table 3.
Parameter Supply Voltage: VCC to GND IMODP, IMODN to GND DATAP, DATAN to GND All Other Pins ESD on IMODP/IMODN1 ESD on All Other Pins1 Junction Temperature Storage Temperature Range
1
Rating -0.3 V to +4.2 V VCC - 1.5 V to 4.5 V VCC - 1.8 V to VCC - 0.4 V -0.3 V to VCC + 0.3 V 200 V HBM 1.5 kV HBM 150C -65C to +125C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ESD CAUTION
HBM = human body model.
Rev. 0 | Page 5 of 20
ADN2531 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
15 DATAN 14 DATAP 13 VCC
PIN 1 INDICATOR
16 VCC
MSET 1 CPA 2 ALS 3 GND 4
12 BSET 11 IBMON 10 IBIAS 9 GND
ADN2531
TOP VIEW (Not to Scale)
VCC 5 IMODN 6 IMODP 7 VCC 8
Figure 3. Pin Configuration
Table 4. Pin Function Descriptions
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Exposed Pad Mnemonic MSET CPA ALS GND VCC IMODN IMODP VCC GND IBIAS IBMON BSET VCC DATAP DATAN VCC EP I/O Input Input Input Power Power Output Output Power Power Output Output Input Power Input Input Power Power Description Modulation Current Control Input Crosspoint Adjust Control Input Automatic Laser Shutdown Negative Power Supply Positive Power Supply Modulation Current Negative Output Modulation Current Positive Output Positive Power Supply Negative Power Supply Bias Current Output Bias Current Monitoring Output Bias Current Control Input Positive Power Supply Data Signal Positive Input Data Signal Negative Input Positive Power Supply Connect to the VCC or GND plane
Rev. 0 | Page 6 of 20
07881-003
NOTES 1. THERE IS AN EXPOSED PAD ON THE BOTTOM OF THE PACKAGE THAT MUST BE CONNECTED TO THE VCC OR GND PLANE.
ADN2531 TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25C, VCC = 3.3 V, crosspoint adjust disabled, unless otherwise noted.
35 30 25
RISE TIME (ps)
10
DETERMINISTIC JITTER (ps p-p)
8
10.7GBPS
20 15 10 5 0 10 30 50 IMOD (mA) 70
07881-004
6
11.3GBPS
4
2
10
20
30
40
50 IMOD (mA)
60
70
80
Figure 4. Rise Time vs. IMOD
Figure 7. Deterministic Jitter vs. IMOD
35
1.0 0.9
30 0.8 25
FALL TIME (ps)
RANDOM JITTER (ps rms)
0.7 0.6 0.5 0.4 0.3 0.2
20
15 10 5
0.1
07881-005
10
20
30
40 50 IMOD (mA)
60
70
80
10
20
30
40
50 IMOD (mA)
60
70
80
Figure 5. Fall Time vs. IMOD
Figure 8. Random Jitter vs. IMOD
0 -5
0
-5
DIFFERENTIAL |S22| (dB)
-10
DIFFERENTIAL |S11| (dB)
-10
-15 -20 -25 -30 -35 -40 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 FREQUENCY (GHz)
-15
-20
-25 -30
07881-006
0
2.5
5.0
7.5
10.0
12.5
15.0
FREQUENCY (GHz)
Figure 6. Differential |S11|
Figure 9. Differential |S22|
Rev. 0 | Page 7 of 20
07881-009
-35
07881-008
0
0
07881-007
0
ADN2531
10
30
9
25
DETERMINISTIC JITTER (ps p-p)
8 7 6 5 4 3 2 11.3GBPS 10.7GBPS
RISE TIME (ps)
20
15
10
5
07881-010
-20
0
20 40 TEMPERATURE (C)
60
80
-20
0
20 40 TEMPERATURE (C)
60
80
100
Figure 10. Rise Time vs. Temperature (Worse-Case Conditions, CPA Disabled)
Figure 13. Deterministic Jitter vs. Temperature (Worse-Case Conditions, CPA Disabled)
30
75
25
CROSSPOINT PERCENTAGE (%)
VCC = 3.0V 65 VCC = 3.3V VCC = 3.6V 55
FALL TIME (ps)
20
15
45
10
35
5
25
-20
0
20 40 TEMPERATURE (C)
60
80
07881-011
1.2
1.4 1.6 1.8 2.0 2.2 CPA INPUT PERIPHERAL VOLTAGE (V)
2.4
Figure 11. Fall Time vs. Temperature (Worst-Case Conditions, CPA Disabled)
Figure 14. IMOD Eye Diagram Crosspoint vs. CPA Input Peripheral Voltage and VCC (IMOD = 40 mA)
1.0
75
0.8
CROSSPOINT PERCENTAGE (%)
RANDOM JITTER (ps rms)
65
TA = -40C TA = +85C TA = +25C TA = +100C
0.6
55
45
0.4
35
0.2
25
07881-012
-20
0
20 40 60 TEMPERATURE (C)
80
100
1.0
1.2
1.4 1.6 1.8 2.0 2.2 CPA INPUT PERIPHERAL VOLTAGE (V)
2.4
Figure 12. Random Jitter vs. Temperature (Worst-Case Conditions, CPA Disabled [Worst-Case IMOD = 40 mA])
Figure 15. IMOD Eye Diagram Crosspoint vs. CPA Input Peripheral Voltage and Ambient Temperature (IMOD = 40 mA)
Rev. 0 | Page 8 of 20
07881-015
0 -40
15
07881-014
0 -40
15 1.0
07881-013
0 -40
1 -40
ADN2531
280 260 240 220 200 180
ITOTAL (mA)
135 130 125 120 115 110 105 100 95 90 85 80 75 70 65 60 55 50 45 40 35 30 25 20 15 10 5 0 0 0.2 0.4
100mA I BIAS
RLOAD = 5 RLOAD = 12
160 140 120 100 80 60 40 20 0
50mA I BIAS
IMOD (mA)
RLOAD = 50
10mA I BIAS
20
40 IMOD CURRENT (mA)
60
80
07881-016
0.6 VMSET (V)
0.8
1.0
1.2
Figure 16. Total Supply Current vs. IMOD and IBIAS
Figure 19. IMOD vs.VMSET at Various RLOAD Resistors
12
10 40mA NUMBER OF HITS 8 20mA
1 LEVEL
1 LEVEL
6
CROSSING
4
2
07881-017
0 LEVEL
0 LEVEL
26.5
27.0
27.5
28.0
28.5
29.0
29.5
AVERAGE RISE/FALL TIME (ps)
CH1 17.4mV/DIV 0V
CH2 16.4mV/DIV -6.0mV
Figure 17. Average Rise/Fall Time Distribution vs. IMOD
Figure 20. Electrical Eye Diagram (IMOD = 40 mA, PRBS31 Pattern at 10.3125 Gbps)
120 110 100 90 80 TA = -40C TA = +25C TA = +85C
IBIAS (mA)
70 60 50 40 30 20 10 0 0.1 0.2 0.3
07881-019
0 26.0
07881-119
0
0.4
0.5 0.6 0.7 VBSET (V)
0.8
0.9
1.0
1.1
1.2
Figure 18. IBIAS vs. VBEST at Various Temperatures
07881-018
0
Figure 21. Filtered 10 Gb Ethernet Optical Eye Using NX8346TS DFB (PRBS31 Pattern at 10.3125 Gbps)
Rev. 0 | Page 9 of 20
07881-121
ADN2531 TEST CIRCUIT
VEE VEE 750 VBSET TP1 TP2 GND 10 10nF GND BSET IBMON IBIAS GND Z0 = 50 J2 GND GND Z0 = 50 J3 GND GND DC BLOCK GND GND VCC MSET CPA ALS VCC GND DC BLOCK GND Z0 = 50 DATAN IMODN 50 GND BIAS TEE GND GND BIAS TEE: PICOSECOND PULSE LABS MODEL 5542-219 ADAPTER: PASTERNACK PE9436 2.92mm FEMALE-TO-FEMALE ADAPTER ATTENUATOR: PASTERNACK PE7046-10 2.92mm 10dB ATTENUATOR Z0 = 50 VCC GND VCC GND GND BIAS TEE Z0 = 50 ADAPTER GND Z0 = 50 ADAPTER ATTENUATOR 50 GND ATTENUATOR OSCILLOSCOPE 50 GND VEE
ADN2531
DATAP IMODP
50 200
VMSET VEE VCPA VEE GND GND J8 J5 VEE
10nF
GND VEE
10F GND
Figure 22. High Speed Characterization Circuit
Rev. 0 | Page 10 of 20
07881-021
ADN2531 THEORY OF OPERATION
As shown in Figure 1, the ADN2531 consists of an input stage and two voltage-controlled current sources for bias and modulation. The bias current is available at the IBIAS pin. It is controlled by the voltage at the BSET pin and can be monitored at the IBMON pin. The differential modulation current is available at the IMODP and IMODN pins. It is controlled by the voltage at the MSET pin. The output stage implements the active back-termination circuitry for proper transmission line matching and power consumption reduction. The ADN2531 can drive a load with differential resistance ranging from 5 to 140 . The excellent back-termination in the ADN2531 absorbs signal reflections from the TOSA end of the output transmission lines, enabling excellent optical eye quality to be achieved even when the TOSA end of the output transmission lines is significantly misterminated.
50 50 C
ADN2531
DATAP DATAN
C
DATA SIGNAL SOURCE
Figure 24. AC Coupling the Data Source to the ADN2531 Data Inputs
BIAS CURRENT
The bias current is generated internally using a voltage-to-current converter consisting of an internal operational amplifier and a transistor, as shown in Figure 25.
VCC
ADN2531
IBMON BSET 800 IBIAS IBMON IBIAS
INPUT STAGE
The input stage of the ADN2531 converts the data signal applied to the DATAP and DATAN pins to a level that ensures proper operation of the high speed switch. The equivalent circuit of the input stage is shown in Figure 23.
VCC
07881-024
200
DATAP 50 VCC
200 GND
2
Figure 25. Voltage-to-Current Converter Used to Generate IBIAS
50
07881-022
DATAN
Figure 23. Equivalent Circuit of the Input Stage
The DATAP and DATAN pins are terminated internally with a 100 differential termination resistor. This minimizes signal reflections at the input that could otherwise lead to degradation in the output eye diagram. It is not recommended to drive the ADN2531 with single-ended data signal sources. The ADN2531 input stage must be ac-coupled to the signal source to eliminate the need for matching between the common-mode voltages of the data signal source and the input stage of the driver (see Figure 24). The ac coupling capacitors should have an impedance less than 50 over the required frequency range. Generally, this is achieved using 10 nF to 100 nF capacitors, for more than 1 Gbps operation.
The BSET to IBIAS voltage-to-current conversion factor is set at 100 mA/V by the internal resistors, and the bias current is monitored at the IBMON pin using a current mirror with a gain equal to 1/100. By connecting a 750 resistor between IBMON and GND, the bias current can be monitored as a voltage across the resistor. A low temperature coefficient precision resistor must be used for the IBMON resistor (RIBMON). Any error in the value of RIBMON due to tolerances or drift in its value over temperature contributes to the overall error budget for the IBIAS monitor voltage. If the IBMON voltage is being connected to an ADC for analogto-digital conversion, RIBMON should be placed close to the ADC to minimize errors due to voltage drops on the ground plane. See the Design Example section for example calculations of the accuracy of the IBIAS monitor as a percentage of the nominal IBIAS value.
Rev. 0 | Page 11 of 20
07881-023
ADN2531
The equivalent circuits of the BSET, IBIAS, and IBMON pins are shown in Figure 26 to Figure 28.
VCC VCC BSET 800 200
07881-025
AUTOMATIC LASER SHUTDOWN (ALS)
The ALS pin is a digital input that enables/disables both the bias and modulation currents, depending on the logic state applied, as shown in Table 5. Table 5. ALS Logic States
ALS Logic State High Low Floating IBIAS and IMOD Disabled Enabled Enabled
Figure 26. Equivalent Circuit of the BSET Pin
IBIAS VCC VCC 2k
The ALS pin is compatible with 3.3 V CMOS and LVTTL logic levels. Its equivalent circuit is shown in Figure 30.
VCC
07881-026
100
VCC 100
10
ALS 2k
07881-029
Figure 27. Equivalent Circuit of the IBIAS Pin
VCC VCC 500
42k
Figure 30. Equivalent Circuit of the ALS Pin
MODULATION CURRENT
The modulation current can be controlled by applying a dc voltage to the MSET pin. This voltage is converted into a dc current via a voltage-to-current converter that uses an operational amplifier and a bipolar transistor, as shown in Figure 31.
VCC IMODP 100 IMOD IMODN FROM CPA STAGE MSET 400
100 VCC IBMON
07881-027
Figure 28. Equivalent Circuit of the IBMON Pin
The recommended configuration for the BSET, IBIAS, and IBMON pins is shown in Figure 29.
TO LASER CATHODE L IBIAS IBIAS
ADN2531
BSET GND IBMON RIBMON 750
07881-028
VBSET
ADN2531
GND
Figure 29. Recommended Configuration for BSET, IBIAS, and IBMON Pins
Figure 31. Generation of Modulation Current on the ADN2531
The circuit used to drive the BSET voltage must be able to drive the 1 k input resistance of the BSET pin. For proper operation of the bias current source, the voltage at the IBIAS pin must be between the compliance voltage specifications for this pin over supply, temperature, and bias current range (see Table 1). The maximum compliance voltage is specified for only two bias current levels (10 mA and 100 mA), but it can be calculated for any bias current by VCOMPLIANCE (V) = VCC (V) - 0.75 - 4.4 x IBIAS (A) See the Headroom Calculations section for examples. The function of Inductor L is to isolate the capacitance of the IBIAS output from the high frequency signal path. For recommended components, see Table 6.
The dc current is switched by the data signal applied to the input stage (DATAP and DATAN pins) and gained up by the output stage to generate the differential modulation current at the IMODP and IMODN pins. The output stage also generates the active back-termination, which provides proper transmission line termination. Active back-termination uses feedback around an active circuit to synthesize a broadband termination resistance. This provides excellent transmission line termination while dissipating less power than a traditional resistor passive backtermination. No portion of the modulation current flows in the active back-termination resistance. All of the preset modulation current (IMOD), the range of which is specified in Table 1, flows into the external load.
Rev. 0 | Page 12 of 20
07881-030
200
ADN2531
The equivalent circuits for the MSET, IMODP, and IMODN pins are shown in Figure 32 and Figure 33. The two 50 resistors in Figure 33 represent the active back-termination resistance.
VCC VCC
200 190 180 170 160 150 GAIN (mA/V) 140 130 120 110 100 90 80 70 60 0 10 20 30 40 DIFFERENTIAL RLOAD () 50 60
07881-034
MAXIMUM
MSET 400
07881-031
TYPICAL MINIMUM
200
Figure 32. Equivalent Circuit of the MSET Pin
VCC 50 IMODN IMODP 50 VCC
50
7.7
7.7
07881-032
Figure 35. MSET Voltage to Modulation Current Ratio vs. Differential Load Resistance
Figure 33. Equivalent Circuit of the IMODP and IMODN Pins
The recommended configuration of the MSET, IMODP, and IMODN pins is shown in Figure 34. See Table 6 for recommended components. When the voltage on DATAP is greater than the voltage on DATAN, the modulation current flows into the IMODP pin and out of the IMODN pin, generating an optical Logic 1 level at the TOSA output when the TOSA is connected as shown in Figure 34.
IBIAS VCC L Z0 = 25 IMODP ZL = 100 Z0 = 25 IMODN MSET VMSET GND L L
07881-033
Using the resistance of the TOSA, the user can calculate the voltage range that should be applied to the MSET pin to generate the required modulation current range (see the example in the Applications Information section). The circuit used to drive the MSET voltage must be able to drive the 600 resistance of the MSET pin. To be able to drive 80 mA modulation currents through the differential load, the output stage of the ADN2531 (IMODP and IMODN pins) must be ac-coupled to the load. The voltages at these pins have a dc component equal to VCC and an ac component with single-ended peak-to-peak amplitude of IMOD x 50 . This is the case when the load impedance (RTOSA) is less than 100 differential because the transmission line characteristic impedance sets the peak-topeak amplitude. For the case where RTOSA is greater than 100 , the single-ended, peak-to-peak amplitude is IMOD x RTOSA / 2. For proper operation of the output stage, the voltages at the IMODP and IMODN pins must be between the compliance voltage specifications for this pin over supply, temperature, and modulation current range, as shown in Figure 36. See the Headroom Calculations section for examples of headroom calculations.
VIMODP, VIMODN
ADN2531
L C Z0 = 25
FP/DFB TOSA C Z0 = 25
VCC
VCC
Figure 34. Recommended Configuration for the MSET, IMODP, and IMODN Pins
The ratio between the voltage applied to the MSET pin and the differential modulation current available at the IMODP and IMODN pins is a function of the load resistance value, as shown in Figure 35.
VCC + 1.1V
NORMAL OPERATION REGION VCC
VCC - 1.1V
Figure 36. Allowable Range for the Voltage at IMODP and IMODN
Rev. 0 | Page 13 of 20
07881-035
ADN2531
LOAD MISTERMINATION
Due to its excellent S22 performance, the ADN2531 can drive differential loads that range from 5 to 140 . In practice, many TOSAs have differential resistance not equal to 100 . In this case, with 100 differential transmission lines connecting the ADN2531 to the load, the load end of the transmission lines are misterminated. This mistermination leads to signal reflections back to the driver. The excellent back-termination in the ADN2531 absorbs these reflections, preventing their reflection back to the load. This enables excellent optical eye quality to be achieved even when the load end of the transmission lines is significantly misterminated. The connection between the load and the ADN2531 must be made with 100 differential (50 single-ended) transmission lines so that the driver end of the transmission lines is properly terminated. Considering VBSET/IBIAS = 10 V/A as the conversion factor from VBSET to IBIAS, the dissipated power becomes
V V P = VCC x MSET + I SUPPLY + V IBIAS x BSET 10V / A 5.8 To ensure long-term reliable operation, the ADN2531 junction temperature must not exceed 150C, as specified in Table 3. For improved heat dissipation, the module case can be used as a heat sink, as shown in Figure 38.
THERMAL COMPOUND MODULE CASE
TTOP
DIE PACKAGE
TJ TPAD
THERMOCOUPLES
CROSSPOINT ADJUST
The crossing level in the output electrical eye diagram can be adjusted between 35% and 65% using the crosspoint adjust (CPA) control input. This can be used to compensate for asymmetry in the laser response and to optimize the optical eye mask margin. The CPA input is a voltage-control input, and a plot of eye crosspoint vs. CPA control voltage is shown in Figure 14 and Figure 15 in the Typical Performance Characteristics section. The equivalent circuit for the CPA pin is shown in Figure 37. To disable the crosspoint adjust function and set the eye crossing to 50%, the CPA pin should be tied to VCC.
PCB COPPER PLANE VIAS
Figure 38. Typical Optical Module Structure
A compact optical module is a complex thermal environment, and calculations of device junction temperature using the junction-toambient thermal resistance (JA) of the package do not yield accurate results. The following equation, derived from the model in Figure 39, can be used to estimate the IC junction temperature:
TJ = P x J - PAD x J -TOP + TTOP x J - PAD + TPAD x J -TOP J - PAD + J -TOP
(
)
7k 7k
7k
VCC CPA
07881-036
Figure 37. Equivalent Circuit for CPA Pin
POWER CONSUMPTION
The power dissipated by the ADN2531 is given by
P = VCC V x MSET + I SUPPLY + V IBIAS x I BIAS 5. 8
where: TTOP is the temperature at the top of the package in C. TPAD is the temperature at the package exposed paddle in C. TJ is the IC junction temperature in C. P is the ADN2531 power dissipation in watts. J-TOP is the thermal resistance from the IC junction to the top of the package. J-PAD is the thermal resistance from the IC junction to the exposed paddle of the package.
TTOP
J-TOP
TJ P
TTOP
where: VCC is the power supply voltage. IBIAS is the bias current generated by the ADN2531. VMSET is the voltage applied to the MSET pin. ISUPPLY is the sum of the current that flows into the VCC, IMODP, and IMODN pins when VBSET = VMSET = 0 (see Table 1). VIBIAS is the average voltage on the IBIAS pin.
J-PAD
TPAD TPAD
07881-038
Figure 39. Electrical Model for Thermal Calculations
TTOP and TPAD can be determined by measuring the temperature at points inside the module, as shown in Figure 38. The thermocouples should be positioned to obtain an accurate measurement of the temperatures of the package top and paddle. J-TOP and J-PAD are given in Table 2.
Rev. 0 | Page 14 of 20
07881-037
ADN2531 APPLICATIONS INFORMATION
TYPICAL APPLICATION CIRCUIT
Figure 40 shows a typical application circuit for the ADN2531. The dc voltages applied to the BSET and MSET pins control the bias and modulation currents. The bias current can be monitored as a voltage drop across the 750 resistor connected between the IBMON pin and GND. The dc voltage applied to the CPA pin controls the crosspoint in the output eye diagram. By tying the CPA pin to VCC, the CPA function is disabled. The ALS pin allows the user to turn the bias and modulation currents on and off, depending on the logic level applied to the pin. The data signal source must be connected to the DATAP and DATAN pins of the ADN2531 using 50 transmission lines. The modulation current outputs, IMODP and IMODN, must be connected to the load (TOSA) using 100 differential (50 single-ended) transmission lines. Table 6 provides a list of recommended components for the ac coupling interface between the ADN2531 and the TOSA. The reference circuit can support up to 11.3 Gbps applications, and the low frequency cutoff performance is dependent on the dc blocking capacitance and the transmission line impedance. For additional applications information and optical eye diagram performance data, consult the relevant application notes on the ADN2531 product page at www.analog.com.
Table 6. Recommended Components
Component R1, R2 R3, R4 R13, R14 C3, C4 L6, L7 L2, L3 L1, L4, L5, L8 10 H Value 110 300 Varies 100 nF 160 nH Description 0603 size resistor 0603 size resistor The resistor value and size are TOSA load impedance dependent 0402 size capacitor, Phycomp 223878719849 0603 size inductor, Murata LQW18ANR16 0603 size chip ferrite bead, Murata BLM18HG601 0805 size inductor, Murata LQM21FN100M70L
GND
VCC R5 750 GND C5 10nF VCC L1 R1 L8
C8 100nF VCC
BSET
TP1
R4
VCC Z0 = 50 DATAP C1
BSET IBMON IBIAS GND VCC VCC
VCC Z0 = 50
L2
R14
L7 Z0 = 50
DATAP
IMODP
ADN2531
Z0 = 50 DATAN C2 VCC VCC MSET VCC GND VCC DATAN IMODN
GND Z0 = 50 GND L3
C4 TOSA Z0 = 50 C3 R13 L6
CPA
ALS
VCC MSET +3.3V VCC C7 20F GND CPA ALS C6 10nF GND VCC VCC
07881-039
L4
R2
L5
R3
Figure 40. Typical ADN2531 Application Circuit
Rev. 0 | Page 15 of 20
ADN2531
LAYOUT GUIDELINES
Due to the high frequencies at which the ADN2531 operates, care should be taken when designing the PCB layout to obtain optimum performance. For example, use controlled impedance transmission lines for high speed signal paths, and keep the length of transmission lines as short as possible to reduce losses and pattern-dependent jitter. In addition, the PCB layout must be symmetrical, both on the DATAP and DATAN inputs and on the IMODP and IMODN outputs, to ensure a balance between the differential signals. Furthermore, all VCC and GND pins must be connected to solid copper planes by using low inductance connections. When these connections are made through vias, multiple vias can be connected in parallel to reduce the parasitic inductance. Each GND pin must be locally decoupled to VCC with high quality capacitors (see Figure 40). If proper decoupling cannot be achieved using a single capacitor, use multiple capacitors in parallel for each GND pin. A 20 F tantalum capacitor must be used as the general decoupling capacitor for the entire module. For recommended PCB layouts, including those suitable for the SFP+ and XFP modules, contact sales. For guidelines on the surface-mount assembly of the ADN2531, see the AN-772 Application Note, A Design and Manufacturing Guide for the Lead Frame Chip Scale Package (LFCSP), on www.analog.com. Therefore, VIBIAS = 1.32 V > 0.6 V, which satisfies the requirement The maximum voltage at the IBIAS pin must be less than the maximum IBIAS compliance specification as described by
VCOMPLIANCE_MAX = VCC - 0.75 - 4.4 x IBIAS (A)
For this example,
VCOMPLIANCE_MAX = VCC - 0.75 - 4.4 x 0.04 = 2.374 V
Therefore, VIBIAS = 1.32 V < 2.374 V, which satisfies the requirement. To calculate the headroom at the modulation current pins (IMODP and IMODN), the voltage has a dc component equal to VCC due to the ac-coupled configuration and a swing equal to IMOD x 50 because RTOSA is less than 100 . For proper operation of the ADN2531, the voltage at each modulation output pin should be within the normal operation region shown in Figure 36. Assuming the dc voltage drop across L1, L2, L3, and L4 is 0 V and IMOD is 40 mA, the minimum voltage at the modulation output pins is equal to
VCC - (IMOD x 12)/2 = VCC - 0.24 V
Therefore, VCC - 0.24 > VCC - 1.1 V, which satisfies the requirement. The maximum voltage at the modulation output pins is equal to
VCC + (IMOD x 12)/2 = VCC + 0.24 V
DESIGN EXAMPLE
Assuming that the impedance of the TOSA is 12 , the forward voltage of the laser at low current is VF = 1.5 V, IBIAS = 40 mA, IMOD = 40 mA, and VCC = 3.3 V, this design example calculates
* * *
Therefore, VCC + 0.24 < VCC + 1.1 V, which satisfies the requirement. Headroom calculations must be repeated for the minimum and maximum values of the required IBIAS and IMOD ranges to ensure proper device operation over all operating conditions.
The headroom for the IBIAS, IMODP, and IMODN pins. The typical voltage required at the BSET and MSET pins to produce the desired bias and modulation currents. The IBIAS monitor accuracy over the IBIAS current range.
BSET and MSET Pin Voltage Calculations
To set the desired bias and modulation currents, the BSET and MSET pins of the ADN2531 must be driven with the appropriate dc voltage. The voltage range required at the BSET pin to generate the required IBIAS range can be calculated using the BSET voltage to IBIAS gain specified in Table 1. Assuming that IBIAS = 40 mA and that IBIAS/VBSET = 100 mA/V (which is the typical IBIAS/VBSET ratio), the BSET voltage is given by
VBSET = I BIAS (mA) 100 mA/V = 40 = 0.4 V 100
Headroom Calculations
To ensure proper device operation, the voltages on the IBIAS, IMODP, and IMODN pins must meet the compliance voltage specifications in Table 1. Considering the typical application circuit shown in Figure 40, the voltage at the IBIAS pin can be written as
VIBIAS = VCC - VF - (IBIAS x RTOSA) - VLA
where: VCC is the supply voltage. VF is the forward voltage across the laser at low current. RTOSA is the resistance of the TOSA. VLA is the dc voltage drop across L5, L6, L7, and L8. For proper operation, the minimum voltage at the IBIAS pin should be greater than 0.6 V, as specified by the minimum IBIAS compliance specification in Table 1. Assuming that the voltage drop across the 50 transmission lines is negligible and that VLA = 0 V, VF = 1.5 V, and IBIAS = 40 mA,
VIBIAS = 3.3 - 1.5 - (0.04 x 12) = 1.32 V
The BSET voltage range can be calculated using the required IBIAS range and the minimum and maximum BSET voltage to IBIAS gain values specified in Table 1. The voltage required at the MSET pin to produce the desired modulation current can be calculated using
V MSET = I MOD K
where K is the MSET voltage to IMOD ratio.
Rev. 0 | Page 16 of 20
ADN2531
The value of K depends on the actual resistance of the TOSA and can be obtained from Figure 35. For a TOSA resistance of 12 , the typical value of K is 110 mA/V. Assuming that IMOD = 40 mA and using the preceding equation, the MSET voltage is given by
V MSET 40 = = = 0.36 V 110 mA/V 110 I MOD (mA) This example assumes that the nominal value of IBIAS is 40 mA and that the IBIAS range for all operating conditions is 10 mA to 80 mA. The accuracy of the IBIAS to IBMON ratio is given in Table 1 and is plotted in Figure 41. Referring to Figure 41, the IBMON output current accuracy is 4.3% for the minimum IBIAS of 10 mA and 3.0% for the maximum IBIAS value of 80 mA. The accuracy of the IBMON output current as a percentage of the nominal IBIAS is given by
The MSET voltage range can be calculated using the required IMOD range and the minimum and maximum K values. These values can be obtained from the minimum and maximum curves in Figure 35.
IBMON _ Accuracy MIN = 10 mA for the minimum IBIAS value, and by
4.3 100 x = 1.075% 100 40 mA
IBIAS Monitor Accuracy Calculations
6
ACCURACY OF IBIAS TO IBMON RATIO (%)
IBMON _ Accuracy MAX = 80 mA
5
3.0 100 x = 6.0% 100 40 mA
4
3
2
for the maximum IBIAS value. This gives a worse-case accuracy for the IBMON output current of 6.0% of the nominal IBIAS value over all operating conditions. The IBMON output current accuracy numbers can be combined with the accuracy numbers for the 750 IBMON resistor (RIBMON) and any other error sources to calculate an overall accuracy for the IBMON voltage.
1
0
20
40 IBIAS (mA)
60
80
100
Figure 41. Accuracy of IBIAS to IBMON Ratio
07881-040
0
Rev. 0 | Page 17 of 20
ADN2531 OUTLINE DIMENSIONS
3.00 BSC SQ 0.45 PIN 1 INDICATOR TOP VIEW 2.75 BSC SQ 0.50 BSC 12 MAX 0.90 0.85 0.80 SEATING PLANE 0.30 0.23 0.18 0.80 MAX 0.65 TYP 0.05 MAX 0.02 NOM 0.20 REF
071708-A
0.60 MAX
BOTTOM VIEW
0.50 0.40 0.30
PIN 1 INDICATOR
*1.65 1.50 SQ 1.35
13 12
16
1
EXPOSED PAD
9 8
4 5
0.25 MIN
1.50 REF FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET.
*COMPLIANT TO JEDEC STANDARDS MO-220-VEED-2 EXCEPT FOR EXPOSED PAD DIMENSION.
Figure 42. 16-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 3 mm x 3 mm Body, Very Thin Quad (CP-16-3) Dimensions shown in millimeters
ORDERING GUIDE
Model ADN2531ACPZ-WP 1 ADN2531ACPZ-R21 ADN2531ACPZ-R71 EVAL-ADN2531-NTZ1 EVAL-ADN2531-NPZ1
1
Temperature Range -40C to +100C -40C to +100C -40C to +100C
Package Description 16-Lead LFCSP_VQ, 50-Piece Waffle Pack 16-Lead LFCSP_VQ, 250-Piece Reel 16-Lead LFCSP_VQ, 1,500-Piece Reel Optical Evaluation Board Without Laser Populated Optical Evaluation Board with Laser Populated
Package Option CP-16-3 CP-16-3 CP-16-3
Branding F0K F0K F0K
Z = RoHS Compliant Part.
Rev. 0 | Page 18 of 20
ADN2531 NOTES
Rev. 0 | Page 19 of 20
ADN2531 NOTES
(c)2009 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D07881-0-9/09(0)
Rev. 0 | Page 20 of 20

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